Author(s): Luo, Q (Luo, Qian); Yao, CH (Yao, Chunhe); Ning, K (Ning, Ke); Zheng, XM (Zheng, Xuemin); Zhao, MX (Zhao, Mingxin); Cheng, L (Cheng, Li); Yu, SM (Yu, Shuangming); Liu, J (Liu, Jian); Wu, NJ (Wu, Nanjian); Liu, LY (Liu, Liyuan)

Source: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS Volume: 69 Issue: 9 Pages: 3884-3888 DOI: 10.1109/TCSII.2022.3181161 Published: SEP 2022

Abstract: Vision chips perform image capture and real-time intelligent image processing by integrating an imager and a vision processor on a single chip, having broad application prospects. This brief proposes a programmable and flexible vision processor with a dual-issue micro-architecture. The processor consists of a reconfigurable vector unit, a flexible memory access network, and a non-maximum suppression (NMS) block. It can efficiently implement both deep neural network (DNN) and traditional computer vision (CV) algorithms. The vector unit performs single-instruction multiple-vector (SIMV) parallel operations with reconfigurable vector width. The flexible memory access network adaptively supports multiple vector operations under different vector widths. A four-MAC processing element (PE) in the vector unit is designed to increase computational power and data reuse rate. The NMS block can speed up the object location processing of the detection networks. The chip is fabricated in a 28nm process. The experimental results show that the maximum clock frequency, peak performance, and peak energy efficiency are 600MHz, 1.2TOPS, and 2.03TOPS/W, respectively. The Mobilenet-Vl processing achieves a throughput of 404 fps under a 256x224 image size and an 87.15%(top-5) accuracy on the ImageNet dataset.

Accession Number: WOS:000848263100056

ISSN: 1549-7747

eISSN: 1558-3791

Full Text: https://ieeexplore.ieee.org/document/9790848