A Provisional Labels-Reduced, Real-Time Connected Component Labeling Algorithm for Edge Hardware
Author(s): Zhou, HT (Zhou, Hongtao); Dou, RJ (Dou, Runjiang); Cheng, L (Cheng, Li); Liu, J (Liu, Jian); Wu, NJ (Wu, Nanjian)
Source: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS Volume: 69 Issue: 6 Pages: 2997-3001 DOI: 10.1109/TCSII.2022.3152783 Published: JUN 2022
Abstract: Connected component labeling (CCL) is an important operation in computer vision tasks, widely used for real-time image processing on edge hardware. The existing connected component labeling algorithms always generate plenty of provisional labels. Solving the equivalence of provisional labels needs much memory access and processing time. The greater difficulty is that the processing time varies with the number and shape of the connected components. To solve the problems, this brief proposes a new two-scan CCL algorithm. It consists of novel provisional label predicting and provisional label assignment methods based on predicting table, linked lists, and equivalent table. The provisional label predicting method reduces the number of provisional labels effectively. The provisional label assignment method can implement quickly the assignment operation of CCL by combination of the first scan and the second scan with fixed processing time. We have implemented the proposed algorithm on Field Programmable Gate Arrays (FPGA) for raster scan images. The results show that its processing speed can achieve 726fps@225MHz for 640x480 image resolution, and its resource utilization is less than 15% of compared implementation. It is suitable for real-time edge applications. Compared with other algorithms, the proposed algorithm reduces provisional labels efficiently and completes the CCL operation with a fixed number of iterations. Therefore, it shortens processing time and makes the processing time constant.
Accession Number: WOS:000804726500089
ISSN: 1549-7747
eISSN: 1558-3791
Full Text: https://ieeexplore.ieee.org/document/9717283