Author(s): Zheng, XM (Zheng, Xuemin); Cheng, L (Cheng, Li); Zhao, MX (Zhao, Mingxin); Luo, Q (Luo, Qian); Li, HL (Li, Honglong); Dou, RJ (Dou, Runjiang); Yu, SM (Yu, Shuangming); Wu, NJ (Wu, Nanjian); Liu, LY (Liu, Liyuan)

Source: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS Volume: 69 Issue: 6 Pages: 2957-2961 DOI: 10.1109/TCSII.2022.3156945 Published: JUN 2022

Abstract: Nowadays, the vision chip bridging sensing and processing has been extensively employed in high-speed image processing, owing to its excellent performance, low power consumption, and economical cost. However, there is a dilemma in designing processors to support conventional computer vision algorithms and neural networks since the two algorithms have a non-trivial trade-off in proposing a unified architecture. By analyzing computation properties, we propose a novel hierarchical parallel vision processor (ViP) for hybrid vision chips to accelerate both traditional computer vision (CV) and neural network (NN). The ViP architecture includes three parallelism levels: PE for pixel-centric, computing core (CC) for block, and vision core (VC) for global. PEs contain dedicated computing units and data paths for convolution operations without degrading its flexibility. Each CC is driven by customized SIMD instructions and can be dynamically connected for meeting block parallelism requirements. ViP is fabricated in 65nm CMOS technology and achieves a peak performance of 614.4 GOPS and an energy efficiency of 640 GOPS/W at 200 MHz clock frequency. Notably, several experiments on CV and NN are performed, illustrating an ultra-low latency in executing hybrid algorithms.

Accession Number: WOS:000804726500081

ISSN: 1549-7747

eISSN: 1558-3791

Full Text: https://ieeexplore.ieee.org/document/9729402