Author(s): Liu, F (Liu, Feng); Qiao, RX (Qiao, Ruixiu); Chen, G (Chen, Gang); Gong, GL (Gong, Guoliang); Lu, HX (Lu, Huaxiang)

Source: IEICE ELECTRONICS EXPRESS Article Number: 20220124 DOI: 10.1587/elex.19.20220124 Early Access Date: APR 2022

Abstract: This work proposes a high-performance reconfigurable CNN accelerator architecture, called CASSANN-v2, which can achieve 1TOPS peak performance at 1GHz. CASSANN-v2 provides the function of on-chip SRAM memory real-time adaptive tuning by parameter configuration to reduce the intermediate output data transmission to further exploit the acceleration performance. The system simulation results show that CASSANN-v2 exhibits excellent performance on VGG-16 and ResNet-18 inference, with a throughput of 1009.54GOPS and 923.24GOPS at 1GHz, which achieved 98.59% and 90.20% average processing element utilization, respectively. Compared with state-of-the-art accelerator works, CASSANN-v2 improves the resource utilization by 2.02x in VGG-16 and L35x in ResNet-18.

Accession Number: WOS:000784998500001

ISSN: 1349-2543

Full Text: https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_19.20220124/_article