Author(s): Hao, Qinfen; Qin, Mengyuan; Qi, Nan; Xue, Haiyun; Han, Meng; Li, Xiaolin; Hao, Kai; Niu, Xingmao; Xiao, Limin; Fan, Dongrui; Kurata, Kazuhiko

Source: IEEE PHOTONICS TECHNOLOGY LETTERS Volume: 33 Issue: 16 Pages: 852-855 DOI: 10.1109/LPT.2021.3084945 Published: AUG 15 2021

Abstract: With the rapid growth of electronic chip's performance, electric signal limits chip I/O in power consumption, reachability, and signal quality. In this letter, we propose a new chip-let architecture for chip-level optical interconnect. An optic I/O chip-let including an ultra-small optic transceiver and electronic components is implemented. Our analysis shows that the optical interconnect based on this architecture can achieve 1/3 power consumption and 1/2 area compared with traditional board-level optical interconnect in Ethernet NIC application. By adopting the architecture we proposed, the optic I/O chip-let can support any payload IC such as CPU, GPU, switch to have optic I/O.

Accession Number: WOS:000678334400014

ISSN: 1041-1135

eISSN: 1941-0174

Full Text: https://ieeexplore.ieee.org/document/9444461