Author(s): Ma, KN (Ma, Kainan); Liu, M (Liu, Ming); Li, T (Li, Tao); Yin, YB (Yin, Yibo); Chen, HD (Chen, Hongda)

Source: ELECTRONICS Volume: 9 Issue: 11 Article Number: 1900 DOI: 10.3390/electronics9111900 Published: NOV 2020

Abstract: Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm(2) at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.

Accession Number: WOS:000593501100001

eISSN: 2079-9292

Full Text: https://www.mdpi.com/2079-9292/9/11/1900