Wang, Tengxiao; Tian, Min; Wang, Haibing; Zhong, Zhengqing; He, Junxian; Tang, Fang; Zhou, Xichuan; Lin, Yingcheng; Yu, Shuang-Ming; Liu, Liyuan; Shi, Cong

Source: IEEE Transactions on Biomedical Circuits and Systems, p 1-16, 2024; ISSN: 19324545, E-ISSN: 19409990; DOI: 10.1109/TBCAS.2024.3412908; Publisher: Institute of Electrical and Electronics Engineers Inc.

Articles not published yet, but available online Article in Press

Author affiliation:

School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China

State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China

Abstract:

This paper presents a digital edge neuromorphic spiking neural network (SNN) processor chip for a variety of edge intelligent cognitive applications. This processor allows high-speed, high-accuracy and fully on-chip spike-timing-based multi-layer SNN learning. It is characteristic of hierarchical multi-core architecture, event-driven processing paradigm, meta-crossbar for efficient spike communication, and hybrid and reconfigurable parallelism. A prototype chip occupying an active silicon area of 7.2 mm was fabricated using a 65-nm 1P9M CMOS process. when running a 256-256-256-256-200 4-layer fully-connected SNN on downscaled 16 × 16 MNIST images. it typically achieved a high-speed throughput of 802 and 2270 frames/s for on-chip learning and inference, respectively, with a relatively low power dissipation of around 61 mW at a 100 MHz clock rate under a 1.0V core power supply, Our on-chip learning results in comparably high visual recognition accuracies of 96.06%, 83.38%, 84.53%, 99.22% and 100% on the MNIST, Fashion-MNIST, ETH-80, Yale-10 and ORL-10 datasets, respectively. In addition, we have successfully applied our neuromorphic chip to demonstrate high-resolution satellite cloud image segmentation and non-visual tasks including olfactory classification and textural news categorization. These results indicate that our neuromorphic chip is suitable for various intelligent edge systems under restricted cost, energy and latency budgets while requiring in-situ self-adaptative learning capability.