第127期:Pixel Circuit Level Dynamic Range Extension Technique & Recent Researches on Smart Image Sensor for 3-D Range Finding
日本东京大学的Makoto Ikeda将于2010年7月8日来我所学术交流,并在“黄昆半导体科学技术论坛”上作第127期报告,望相关领域的各位老师及同学积极参加!
报告题目: Pixel Circuit Level Dynamic Range Extension Technique & Recent Researches on Smart Image Sensor for 3-D Range Finding
报告时间: 2010年7月8日(星期四)上午10:00
报告地点: 中国科学院半导体研究所学术沙龙室
报告人: Makoto Ikeda (University of Tokyo, Japan)
Abstract:In this talk, I will classify techniques to enhance dynamic range from the pixel level standpoint. Dynamic range in pixel level is simply determined by full-well capacity and S/N of pixel value readout. To enhance dynamic range, (1) adjusting well capacity, by changing photo-gate vias or connecting over flow capacitance (special domain); (2) adaptive charge skimming using controlled charge injection into pixel well capacitance (signal level domain); (3) adaptive integration time control using adaptive ramp functions or conditional resetting of saturated pixels (time domain); (4) pixel level signal to frequency conversion, time to saturation conversion or pixel level sigma-delta ADC or time domain ADC (time domein); (5) pixel level logarithmic compression using MOS diodes or lateral overflow gates (signal level domain).In addition, I will briefly overview current researches on smart image sensors for 3-D range finding in my lab.
报告人简介:Xiaobo Makoto Ikeda received his BE, ME, and PhD in Electronic Engineering from the University of Tokyo, Japan, in 1991, 1993, and 1996, respectively. He joined EE department of the University of Tokyo as a research associate in 1996, and joined VLSI Design and Education Center(VDEC), the University of Tokyo in the same year. He continues to work for VDEC for more than 14 years for supporting Japanese academia to design and fabricate LSIs. He is currently an associate professor at both VDEC and EE department of the University of Tokyo. His research interests include smart image sensor design and high-speed, and real-time 3D capture with the smart image sensors, and dependable digital circuits designs. He has served program committee members of ISSCC, VLSI Circuits Symposium, A-SSCC, ICCAD, ICFPT, FPL, ISQED and COOL Chips, and he also serves as FE Regional Committee Vice Chair, and Executive Committee member of ISSCC and TPC Chair of COOL Chips.
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